STM32L152 – Clock Registers

Clock Register Summary
Control and Callibration
RCC-CR Control Register Description #Define
RTCPRE RTC and LCD Prescaller RCC_CR_RTCPRE_0 (0x2)
RCC_CR_RTCPRE_1 (0x4)
CSSON Clock security System RCC_CR_CSSON
PLLRDY PLL clock ready flag RCC_CR_PLLRDY
PLLON PLL Enable RCC_CR_PLLON
HSEBYP HSE clock bypass RCC_CR_HSEBYP
HSERDY HSE clock ready flag RCC_CR_HSERDY
HSEON HSE clock enable RCC_CR_HSEON
MSIRDY MSI clock ready flag RCC_CR_MSIRDY
MSION MSI clock enable RCC_CR_MSION
HSIRDY HSI Ready flag RCC_CR_HSIRDY
HSION HSI enable RCC_CR_HSION
RCC_CSR Control and Status Register
LPWRRSTF: Low Power reset flag RCC_CSR_LPWRRSTF
WWDGRSTF: Window watchdog reset flag RCC_CSR_LPWRRSTF
IWDGRSTF: Independant watchdog reset flag RCC_CSR_LPWRRSTF
SFTRSTF: Software Reset Flag RCC_CSR_SFTRSTF
PORRSTF: POR/PDR reset flag RCC_CSR_SFTRSTF
PINRSTF: PIN reset flag RCC_CSR_SFTRSTF
OBLRSTF Options bytes loaded reset flag RCC_CSR_SFTRSTF
RMVF: Remove Reset flag RCC_CSR_SFTRSTF
RTCRST: RTC software reset RCC_CSR_RTCRST
RTCEN: RTC Enable RCC_CSR_RTCEN
RTCSEL RTC & LCD clock select RCC_CSR_RTCSEL_LSE
RCC_CSR_RTCSEL_LSI
RCC_CSR_RTCSEL_HSE
LSECSSD: Clock Security fail detect RCC_CSR_RTCEN
LSECSSON LSE Clock Security On RCC_CSR_RTCEN
LSEBYP: LSE Bypass RCC_CSR_RTCEN
LSERDY: LSE Ready flag RCC_CSR_LSERDY
LSEON: LSE Onable RCC_CSR_LSEON
LSIRDY: LSI Ready Flag RCC_CSR_LSIRDY
LSION: LSI Enable RCC_CSR_LSION
RCC_CFGR Clock configuration register
MCOPRE Microcontroller clock output prescaller RCC_CFGR_MCOPRE_DIV1
RCC_CFGR_MCOPRE_DIV2
RCC_CFGR_MCOPRE_DIV4
RCC_CFGR_MCOPRE_DIV8
RCC_CFGR_MCOPRE_DIV16
MCOSEL Micocontroller output selection
Pin PA8 on the STM32L152
RCC_CFGR_MCOSEL_HSI
RCC_CFGR_MCOSEL_HSE
RCC_CFGR_MCOSEL_MSI
RCC_CFGR_MCOSEL_PLL
RCC_CFGR_MCOSEL_LSI
RCC_CFGR_MCOSEL_LSE
RCC_CFGR_MCOSEL_SYSCLOCK
PLLDIV PLL output devision RCC_CFGR_PLLDIV_0
RCC_CFGR_PLLDIV_1
PLLMUL PLL clock multiplier factor RCC_CFGR_PLLMUL3
RCC_CFGR_PLLMUL4
RCC_CFGR_PLLMUL6
RCC_CFGR_PLLMUL8
RCC_CFGR_PLLMUL12
RCC_CFGR_PLLMUL16
RCC_CFGR_PLLMUL24
RCC_CFGR_PLLMUL32
RCC_CFGR_PLLMUL48
PLLSRC PLL entry clock source RCC_CFGR_PLLSRC_HSI
RCC_CFGR_PLLSRC_HSE
PPREE2 APB high-speed prescaler
PPRE1 APB low-speed prescaller RCC_CFGR_PPRE1_DIV1
RCC_CFGR_PPRE1_DIV2
RCC_CFGR_PPRE1_DIV4
RCC_CFGR_PPRE1_DIV8
RCC_CFGR_PPRE1_DIV16
HPRE AHB prescaller RCC_CFGR_HPRE_DIV1
RCC_CFGR_HPRE_DIV2
RCC_CFGR_HPRE_DIV4
RCC_CFGR_HPRE_DIV8
RCC_CFGR_HPRE_DIV16
RCC_CFGR_HPRE_DIV64
RCC_CFGR_HPRE_DIV128
RCC_CFGR_HPRE_DIV256
RCC_CFGR_HPRE_DIV512
SWS System clock status RCC_CFGR_SWS_MSI
RCC_CFGR_SWS_HSI
RCC_CFGR_SWS_HSE
RCC_CFGR_SWS_PLL
SW System clock switch RCC_CFGR_SW_MSI
RCC_CFGR_SW_HSE
RCC_CFGR_SW_HSI
RCC_CFGR_SW_PLL
RCC_AHBRSTR AHB peripheral reset register
These flags hold the peripheral in a reset state until cleared.
Check that your device has all the ports described here– this will depend on the pin count
Covers : ASE, CSC, GPIO, DMA and FLIT
AESRST AES reset
Only on STM32L16 devices
N/A
DMA2RST DMA 2 reset RCC_AHBRSTR_DMA2RST
DMA1RST DMA 1 reset RCC_AHBRSTR_DMA1RST
FLITRST FLIT reset
(Flash)
RCC_AHBRSTR_FLITFRST
CRCRST CRC reset RCC_AHBRSTR_CRCRST
GPIOGRST Reset GPIO Port RCC_AHBRSTR_GPIOGRST
GPIOFRST Reset GPIO Port RCC_AHBRSTR_GPIOFRST
GPIOHRST Reset GPIO Port RCC_AHBRSTR_GPIOHRST
GPIOERST Reset GPIO Port RCC_AHBRSTR_GPIOERST
GPIODRST Reset GPIO Port RCC_AHBRSTR_GPIODRST
GPIOCRST Reset GPIO Port RCC_AHBRSTR_GPIOCRST
GPIOBRST Reset GPIO Port RCC_AHBRSTR_GPIOBRST
GPIOARST Reset GPIO Port RCC_AHBRSTR_GPIOARST
RCC_APB2LPENR Peripheral clock enable (Low power register)
This register is used to allow clocks for these peripherals to be enabled during sleep mode
USART1LPEN USART 1 Clock enable during sleep mode RCC_APB2LPENR_USART1LPEN
SPI1LPEN SPI clock enable during sleep mode RCC_APB2LPENR_SPI1LPEN
SDIOLPEN SDIO clock enable during sleep mode Only on cat.4 devices
ADC1LPEN ACD 1 clock enabled during sleep mode RCC_APB2LPENR_ADC1LPEN
TIM11LPEN Timer 11 clock enabled during sleep mode RCC_APB2LPENR_TIM11LPEN
TIM10LPEN Timer 10 clock enabled during sleep mode RCC_APB2LPENR_TIM10LPEN
TIM9LPEN Timer 9 clock enabled during sleep mode RCC_APB2LPENR_TIM9LPEN
SYSCFGLPEN System configuration controller clock
enabled during sleep mode
RCC_APB2LPENR_SYSCFGLPEN
RCC_APB1LPENR APB 1 peripheral clock enable (in low power mode)
This register is used to allow clocks for these peripherals to be enabled during sleep mode
COMPLPEN Comparitor clock enable during sleep RCC_APB1LPENR_COMPLPEN
DACLPEN DAC clock enable during sleep RCC_APB1LPENR_DACLPEN
PWRLPEN Power interface clock enable during sleep RCC_APB1LPENR_PWRLPEN
USBLPEN USB clock enable during sleep RCC_APB1LPENR_USBLPEN
I2C2LPEN I2C clock enable during sleep RCC_APB1LPENR_I2C2LPEN
I2C1LPEN I2C clock enable during sleep RCC_APB1LPENR_I2C1LPEN
UART5LPEN UART clock enable during sleep RCC_APB1LPENR_USART5LPEN
UART4LPEN UART clock enable during sleep RCC_APB1LPENR_USART4LPEN
UART3LPEN UART clock enable during sleep RCC_APB1LPENR_USART3LPEN
UART2LPEN UART clock enable during sleep RCC_APB1LPENR_USART2LPEN
SPI3LPEN SPI clock enable during sleep RCC_APB1LPENR_SPI3LPEN
SPI2LPEN SPI clock enable during sleep RCC_APB1LPENR_SPI2LPEN
WWDGLPEN Watchdog clock enable during sleep RCC_APB1LPENR_WWDGLPEN
LCDLPEN LCD clock enable during sleep RCC_APB1LPENR_LCDLPEN
TIM7LPEN Timer 7 clock enable during sleep RCC_APB1LPENR_TIM7LPEN
TIM6LPEN Timer 6 clock enable during sleep RCC_APB1LPENR_TIM6LPEN
TIM5LPEN Timer 5 clock enable during sleep RCC_APB1LPENR_TIM5LPEN
TIM4LPEN Timer 4 clock enable during sleep RCC_APB1LPENR_TIM4LPEN
TIM3LPEN Timer 3 clock enable during sleep RCC_APB1LPENR_TIM3LPEN
TIM2LPEN Timer 2 clock enable during sleep RCC_APB1LPENR_TIM2LPEN